"Digital Design with VHDL "is intended both for students on preliminary courses in Digital Design and practitioners who would like to integrate digital design with VHDL synthesis in the workplace. Its unique approch compbines the principles of digital design with a guide to the use of VHDL. Synthesis issues are discussed and practical guidelines are provided for improving simulation accuracy and performance. The reader is assumed to have some rudimentary knowledge of Boolean algebra and logic gates although the text recaps these basics in an introductory chapter.